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february 2006 ad v an c ed v 1 .1 1 ? 2006 actel corporation core1553BRT-EBR enhanced bit rate 1553 remote terminal product summary intended use ? 1553 enhanced bit rate remote terminal (rt) dma backend interface to external memory direct backend interface to devices space and avionic applications key features supports enhanced bit rate 1553 10 mbps time-multiplexed serial data bus interfaces to external ram or directly to backend device synchronous or asynchronous backend interface encoders and decoders operate off 100 mhz clock protocol control and me mory interface operates off 50 mhz clock interfaces to standard rs485 transceivers programmable mode code and sub-address legality for illegal command support memory address mapping allowing emulation of legacy remote terminals fail-safe state machines fully synchro nous operation supported families proasic ? 3/e proasic plus ? axcelerator ? rtax-s core deliverables netlist version ? compiled rtl simulation model, compliant with actel libero ? integrated design environment (ide) ? netlist compatible with the actel designer place-and-route tool (with and without i/o pads) rtl version ? vhdl or verilog core source code ? synthesis scripts actel-developed testbench (vhdl) development system complete 1553BRT-EBR implementation, implemented in an ax1000 synthesis and simu lation support synthesis: exemplar ? , synplicity ? , design compiler ? , fpga compiler ? simulation: vital-compliant vhdl simulators and ovi-compliant verilog simulators verification and compliance meets requirements of draft sae as5682 standard (2005-10) actel-developed simulation testbench implements a subset of the rt test plan (mil-hdbk-1553a) for protocol verification protocol control deri ved from core1553brt, which is certified to mi l-std-1553b (rt validation test plan mil-hdbk-1553, appendix a) contents general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 core1553BRT-EBR device requirements . . . . . . . . . . . . 4 core1553BRT-EBR verification and compliance . . . . . . 4 core1553BRT-EBR fail-safe state ma chines . . . . . . . . . . 4 enhanced bit rate 1553 bus overview . . . . . . . . . . . . . . 4 i/o signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1553BRT-EBR operation . . . . . . . . . . . . . . . . . . . . . . . . 14 command legalization interface . . . . . . . . . . . . . . . . . 18 bus transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 typical rt systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 transceiver loopback delays . . . . . . . . . . . . . . . . . . . . 25 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . 25 list of changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 datasheet categories . . . . . . . . . . . . . . . . . . . . . . . . . . 26 advanced v1.1
core1553BRT-EBR enhanced bit rate 1553 remote terminal 2 advanced v1.1 general description core1553BRT-EBR provides a complete, dual-redundant 1553 enhanced bit rate (e br) remote terminal (rt) apart from the transceivers required to interfac e to the bus. a typical system implem entation using the core1553BRT-EBR is shown in figure 1 and figure 2 on page 3 . at a high level, core1553BRT-EBR simply provides a set of memory mapped sub-addresses that "receive data written to" or "transmit data read from." the core can be configured to directly connect to synchronous or asynchronous memory devices. alternately, the core can directly connect to the backend devices, removing the need for the memory buffers. if memory is used, the core requires 2,048 words of memory, which can be shared with the local cpu. the core supports all 1553eb r mode codes and allows the user to designate as illegal any mode code or any particular sub-address for both transmit and receive operations. the command legalization can be done within the core or in an ex ternal command legality block via the command legalization interface. figure 1 ? typical core1553BRT-EBR system actel fpga adc memory glue logic backend interface core1553BRT-EBR command illegality block rs485 transceivers command legality block busain busainenn busaouten busaout busbin busbinenn busbouten busbout
core1553BRT-EBR enhanced bit rate 1553 remote terminal advanced v1.1 3 the core consists of six main bloc ks: 1553ebr encoders, 1553ebr decoders, bac kend interface, command decoder, rt controller blocks, and a command legalization block (see figure 2 ). in the core1553BRT-EBR, a single 1553ebr encoder is used. this takes each word to be transmitted and serializes it, after which the signal is manchester encoded. the encoder also incl udes both logic to prevent the rt from transmitting fo r greater than the allowed period and loopback fail logic. the loopback logic monitors the received data and verifies that the core has correctly received every word that it transmits. the output of the encoder is gated with the bus enable signals to select which buses the rt should use to transmit. the core includes two 1553eb r decoders. the decoder takes the serial manchester data received from the bus and extracts the received data words. the decoder requires a 100 mhz clock to extract the data and the clock from the serial stream. the decoder contains a digital phased-lock loop (pll) that generates a recovery clock used to sample the incoming serial data. the data is then deserialized and the 16-bit word decoded. the decoder detects whether a command or data word is received, and also performs manchester encoding and parity error checking. the backend interface for th e core1553BRT-EBR allows a simple connection to a memory device or direct connection to other devices, such as analog-to-digital converters. the access rates to this memory are slow, with one read or write ever y 2 s. the backend interface operates off the internally derived 50 mhz clock, resulting in a read or write every 100 clock cycles. the backend interface can be configured to connect to either synchronous or asynchronous memory devices. this allows the core to be connected to synchronous logic, memory within the fpga, or external asynchronous memory blocks. the core implements a simple sub-address to the memory address mapping function, allo wing the core to be directly connected to a memory block. the core also supports an address mapping function that allows the backend memory map to be modified to emulate legacy 1553ebr remote terminals, therefore minimizing system and software changes when adopting the core1553BRT-EBR. associated with this function is the ability to create a user- specific interrupt vector. the backend interface suppor ts a standard bus request and grant protocol, and provides a wait input to allow the core to interface to slow memory devices. the command decoder and rt controller blocks decode the incoming command words, verifying their legality. the protocol state machin e then responds to the command, transmitting or receiving data or processing a mode code. the core1553BRT-EBR has an internal command legality block that verifies every 1553ebr command word. a separate interface is prov ided that, when enabled, allows the command legality decoder to be implemented outside the core1553BRT-EBR. th is external interface is intended for use with netlist versions of the core. for the rtl version of the core, this interface can be used or the source code can be modified easily to implement this function. figure 2 core1553BRT-EBR rt block diagram backend interface memory 204816 core1553BRT-EBR command legalization command decoder rt protocol controller decoder decoder encoder busa busb
core1553BRT-EBR enhanced bit rate 1553 remote terminal 4 advanced v1.1 core1553BRT-EBR device requirements the core1553BRT-EBR can be implemented in several actel fpga devices. table 1 gives the utilization and performance figures for the core implemented in these devices. the core can operate with a clock of up to 24 mhz. this clock rate is easily met in all actel silicon families noted in table 1 . core1553BRT-EBR verification and compliance the core1553BRT-EBR functiona lity has been verified in simulation and hardware. to fully verify compliance, the core has been implemented on ax1000 and proasic3 parts connected to external transceivers and memory. core1553BRT-EBR fail-safe state machines the logic design of cor e1553BRT-EBR implements fail- safe state machines. all state machines include illegal state detection logic. if a st ate machine should ever enter an illegal state, the core will assert its fsm_error output and the stat e machine will reset. if this occurs, actel recommends that the external system reset the core and also assert the t flag input to inform the bus controller that a serious error has occurred within the remote terminal. the fsm_error output can be left unconnected if the system is not required to detect and report state machines entering illegal states. enhanced bit rate 1553 bus overview enhanced bit rate 1553 is a enhanced data rate mil-std-1553b bus. the data transmission rate has been increased from 1 mb/sec to 10 mb/sec, and the multi- drop bus structure has been replaced with a hub-based point-to-point bus structure. to maintain system compatibility, the data prot ocol and command, status, and data words are identi cal to the mil-std-1553b specification. the bus has a single active bu s controller (bc) and up to 31 remote terminals (rts). for 1553ebr, the bc has up to 31 separate transceivers, each one connected directly to an rt. the bc manages all data transfers on the bus using the command and status protocol. the bus controller initiates every transfer by sending a command word and data if required. the selected rt will respond with a status word and data if required. the 1553ebr command word contains a five-bit rt address, transmit or receive bi t, five-bit sub-address, and five-bit word count. this allows for 32 rts on the bus. however, since rt address 31 is used to indicate a broadcast transfer, only 31 rts may be connected. each rt has 30 sub-addresses reserved for data transfers. the other two sub-addresses (0 and 31) are reserved for mode codes used for bus control functions. data transfers contain up to 32 16-bit data words. mode code command words are used for bus control functions, such as synchronization. table 1 device utilization family comb. seq. total device utilization performance proasic3/e 970 467 1437 a3p250 24% 115/55 mhz proasic plus 1298 467 1765 apa150 29% 105/55 mhz axcelerator 658 463 1121 ax500 14% 173/87 mhz rtax-s 658 463 1121 rtax250s 27% 126/62 mhz note: the performance column shows the maximum clock speed for th e 100 mhz and 50 mhz clock domains for each fpga family.
core1553BRT-EBR enhanced bit rate 1553 remote terminal advanced v1.1 5 message types the 1553ebr bus supports ei ght message transfer types, allowing basic point-to-point and broadcast bc-to-rt data transfers, as well as mode code messages. figure 3 shows the message formats. figure 3 1553ebr message formats bc-to-rt transfer receive command data 0 data . . . data n response time status word rt message gap next command bc bc rt-to-bc transfer transmit command response time status word data 0 data . . . data n rt bc message gap next command bc mode command, no data mode command response time status word message gap next command rt bc bc mode command, rt transmit data mode command response time status word mode data message gap next command rt bc bc mode command, rt receive data mode command mode data response time status word message gap next command rt bc bc broadcast mode command with data mode command mode data message gap next command bc bc broadcast mode command, no data mode command message gap next command bc bc bc-to-all-rts broadcast receive command data 0 data . . . data n message gap next command bc bc
core1553BRT-EBR enhanced bit rate 1553 remote terminal 6 advanced v1.1 word formats there are only three types of words in a 1553ebr message: a command word (cw), a data word (dw), and a status word (sw). each word consists of a 3-bit sync pattern, 16 bits of data, and a parity bit, providing the 20-bit word (see figure 4 ). i/o signal descriptions bit 1 2 3 4 5 6 7 8 9 1011121314151617181920 cw 515 51 sync rt address t/r sub-address word count / mode code p dw 16 1 sync data p sw 5 111 3 111111 sync rt address message error instrumentation service request reserved broadcast received busy sub-system flag dynamic bus acceptance terminal flag parity figure 4 1553ebr word formats table 2 1553ebr bus interface port name type description rtaddr[4:0] in sets the rt address; must not be set at '11111' rtaddrp in rt address parity input. this input should be set high or low to achieve odd parity on the rtaddr and rtaddrp inputs. if rtaddr is set to '00000', the rtaddrp input should be set to '1'. rtaderr out indicates that the rtaddr and rtaddrp inputs have incorrect parity, or broadcast is enabled and the rt address is set to 31; when active (high), the rt is disabled and will ignore all 1553ebr traffic. busainenn out active low enable for the a receiver busain in data input from the a receiver busbinenn out active low enable for the b receiver busbin in data input from the b receiver busaouten out active high transmi tter enable for the a transmitter busaout out data output to the bus a transmitter busbouten out active high transmitte r enable for the b transmitter busbout out data output to the bus b transmitter
core1553BRT-EBR enhanced bit rate 1553 remote terminal advanced v1.1 7 table 3 control and status signals port name type description clk in master 100 mhz clock input clkout100 out 100 mhz clock input routed to an output pin clkout50 out 50 mhz clock used to clock the protocol and memory interface blocks. all core outputs are synchronized to this clock. will be routed on a global network. rstn in asynchronous reset input (active low) srequest in directly controls the service request bit in the 1553ebr status word rtbusy in directly controls the busy bit in the 1553ebr status word ssflag in directly controls the sub-system flag bit in the 1553ebr status word tflag in controls the sub-system flag bit in the 1553ebr status word. can be masked by the "inhibit terminal flag bit" mode code. vword[15:0] in provides the 16-bit vector value for the "transmit vector word" mode command busy out indicates that the core is either receivi ng or transmitting data or handling a mode command cmdsync out pulses high for a single clock cycle when the rt detects the start of a 1553ebr command word (or status word) on the bus. provides an early signal that the rt may be about to receive or transmit data or mode code. msgstart out pulses high for a single cycle when the rt is about to start processing a 1553ebr message whose command has been validated for this rt. syncnow out pulses high for a single clock cycle when the rt receives a "synchronize" command with or without data mode. the pulse occurs just after the 1553ebr command word (sync with no data) or data word (sync with data mode code) has been received. busreset out pulses high for a single clock cycle whenever the rt receives a reset mode command. the core logic will also automatically reset itself on receipt of this command. intout out goes high when data has been received or transmitted or a mode command processed. the reason for the interrupt is provided on intvect. will stay high until intack goes high. if intack is held high, will pulse high for a single clock cycle. intvect[6:0] out a seven-bit value containing the reas on for the interrupt. indicates which sub-address data has been received or transmitted. bit 6 0: bad block received 1: good block received bit 5 0: rx data 1: tx data bits 4:0 sub-address further information can be found by checking th e appropriate transfer status word for the appropriate sub-address. intack in interrupt acknowledge input. when high, resets intout to low. if this input is held high, the intout signal will pulse high for one clock cycle every time an interrupt is generated. memfail out goes high if the core fa ils to read or write data to the backend interface within the required time. this can be caused by the backend failin g to assert memgntn fast enough or asserting memwaitn for too long. clrerr in used to clear memfail and other internal error conditions. must be held high for more than two clock cycles. note: all control inputs except rstn are synchronous and sampled on the rising edge of the internally generated 50 mhz clock (clkout50). all status output s are synchronized to the risi ng edge of the same clock.
core1553BRT-EBR enhanced bit rate 1553 remote terminal 8 advanced v1.1 command legalization interface the core checks the va lidity of all 1553ebr command words. in rtl and netlist versions of the core, the logic may be implemented externally to the core. the command word is provided, and the logic must generate the command valid input. the command legalization interface also provides two st robes that are used to latch the command value to enable it to be used for address mapping and interrupt vector extension functions ( table 4 ). backend interface the backend interface supports both synchronous operation (to the core clock) and asynchronous operation to backend devices ( table 5 on page 9 ). table 4 command legalization interface port name type description useextok in when '0', the core uses its own internal command valid logic, enabling all legal supported mode codes and all sub-addresses. when '1', the core disables its internal lo gic and uses the external cmdokay input for command legality. cmdval[11:0] out active command 11 0: non-broadcast 1: broadcast 10 0: receive 1: transmit [9:5] sub-address [4:0] word count / mode code these outputs are valid throughout the complete 1553ebr message. they can also be used to steer data to particular backend devices. in particular, bit 11 allows non-broadcast and broadcast messages to be differentiated. cmdstb out single clock cy cle pulse that indicates cmdval has changed cmdokay in command word is okay (active high). the ex ternal logic must set this within 2 s from the cmdval output changing. cmdokout out command word is okay output. when useextok = '0', the core outputs its internal command word okay validation signal. addrlat out cmdval address latch enable output (active high) is used to latch the cmdval when it is being used for an address mapping function. addrlat should be connected to the enable of a rising edge clock flip-flop. intlat out cmdval interrupt vector latch enable outpu t (active high) is used to latch the cmdval when it is being used for an extended interrupt vect or function. intlat should be connected to the enable of a rising edge clock flip-flop.
core1553BRT-EBR enhanced bit rate 1553 remote terminal advanced v1.1 9 table 5 backend signals port name type description memreqn out memory request (active low) output. the backend interface requires memory access completion within 1 s of memreq going low to avoid data loss or overrun on the 1553ebr interface.* memgntn in memory grant (active low) input. this input should be synchronous to clk and needs to meet the internal register setup time. this in put may be held low if the core has continuous access to the ram. memwrn out memory write (active low) synchronous mode: this output indicates that data is to be written on the rising clock edge. asynchronous mode: this output will be low for a minimum of one clock period and can be extended by the memwaitn input. the addres s and data are valid one clock cycle before memwrn is active and held for one clock cycle after memwrn goes inactive. memrdn out memory read (active low) synchronous mode: this output indicates that data will be read on the next rising clock edge. this signal is intended as the read signal for synchronous rams. asynchronous mode: this output will be low for a minimum of one clock period and can be extended by the memwaitn input. the address is valid one clock cycle before memrdn is active and held for one clock cycle after memrdn goes inac tive. the data is sampled as memrdn goes high. memcsn out memory chip select (active low). this output has the same timing as memaddr. memwaitn in memory wait (active low) synchronous mode: this input is not used; it should be tied high. asynchronous mode: indicates that the backend is not ready and that the core should extend the read or write strobe period. this input sh ould be synchronized to clk and needs to meet the internal register setup time. it can be permanently held high. memoper[1:0} out indicates the type of memory access being performed 00: data transfer for both data and mode code transfers 01: tsw 10: command word 11: not used memaddr[10:0] out address (active low). memory address output (the sub-address mapping is covered in the memory allocation section) memdout[15:0] out memory data output (active low) memdin[15:0] in memory data input (active low) memcen out control signal enable (active high). this signal is high when th e core is requesting the memory bus and has been granted control. it is intended to enable any tristate drivers that may be implemented on the memory control and address lines. memden out data bus enable (active high ). this signal is high when the core is requesting the memory bus, has been granted control, and is waiting to write data. it is intended to enable any bidirectional drivers that may be im plemented on the memory data bus. note: *the 1 s refers to the time from memreqn being asserted to th e core deasserting its memreqn si gnal. the core has an internal overhead of five clock cycles, and any insert ed wait cycles will also reduce this time.
core1553BRT-EBR enhanced bit rate 1553 remote terminal 10 advanced v1.1 miscellaneous i/o several inputs are used to modify the core functionality to simplify integration in th e application. these inputs should be tied to logic '0' or logic '1', as appropriate ( table 6 ). standard memory address map core1553BRT-EBR requires an external 2,04816 memory device. this memory is split into 64 32-word data buffers. each of the 30 sub-addresses has a receive and a transmit buffer, as shown in table 7 on page 11 . the memory allocated to the unused receive sub- addresses 0 and 31 is used to provide status information back to the rest of the system. at the end of every transfer, a transfer status wo rd (tsw) is written to these locations. table 6 miscellaneous i/os port name type description wrtcmd in when '1', the core will write the 1553e br command word to the locations used for the tsw values. if wrttsw is also enabled, then the co mmand word is written to memory at the start of a message and the tsw value will overwr ite the command word at the end of the message, unless an external address mapping function is used. wrttsw in when '1', the core will write the transfer status word to the memory. when '0', the core disables th e writing of the transfer status word to memory. this is useful for simple rt applications th at do not use memory but have a direct connection to the backend device. extmdata in when '1', the core reads and writes mode code data words to and from the external memory (except for the transmit last command and transmit bit word). the vword input is not used when this input is active. intenbbr in when active '1', the core generates in terrupts when both good and bad 1553ebr messages are received. when inactive '0 ', the core only generates inte rrupts when good messages are received. asyncif in when '1', the backend interface is in asynchronous mode. when '0', the backend interface is in synchronous mode. testtxtout in this input is for test use only. it should be tied low. when high, the rt will transmit more than 32 data words if a transmit data command word is received. this will cause the rt to shut down the transmitter and set the timeout bits in the bit word. bcasten in this input enables broadcast operation. when '1', broadcast operations are enabled. when '0', broadcast messages (i.e., rt address 31) are treated as normal messages. if the rtaddr input is set to 31, then th e rt will respon d to the message. sa30loop in this input alters the ba ckend memory mapping so that sub-address 30 provides automatic loopback ( table 7 on page 11 ). when '0', the rt does not loopback sub-addr ess 30. separate memory buffers are used for transmit and receive data buffers. when '1', the rt maps the tran smit memory buffer for sub-address 30 to the receive memory buffer for sub-address 30, i.e., the upper address line is forced to '0'. fsm_error out this output will go high for a single cloc k cycle if any of the internal state machines enter an illegal state. this output should not go high in normal operation. shou ld it go high, it is recommended that the core be reset.
core1553BRT-EBR enhanced bit rate 1553 remote terminal advanced v1.1 11 if the sa30loop input is set high, the rt maps transmit sub-address 30 to the receive sub-address 30, i.e., the upper address bit is forced to '0'. this provides a loopback sub-address as pe r mil-std-1553ebr, notice 2. the tsw is still written to address 03ee. it should be noted that this is not strictly compliant with the specification since the transm it buffer will contain invalid data if the received command fails, e.g., on a parity error. the transmit buffer should only be updated if the receive command had no errors. to implement this function in full compliance with the sp ecification, the sa30loop input should be tied low, and the rt backend should copy the receive memory buffer to the transmit memory buffer only after the rt signals that the message was received with no errors. when the memory buffer is implemented within the fpga device using dual-port rams, separate receive and transmit ram blocks can be us ed (each as 1 k words), as shown in figure 5 . in these cases, the rx memory is selected when a10 = 0 and the tx memory when a10 = 1. in this case, the sa30loop input must be tied low. table 7 standard memory address map address ram contents notes 000?01f rx transfer status words the core only writes to these addresses (except when sa30loop is high). 020?03f receive sub-address 1 ? 3c0?3df receive sub-address 30 3e0?3ff tx transfer status words 400?41f not used the core only reads from these addresses. 420?43f tx transfer sub-address 1 ? 7c0?7df tx transfer sub-address 30 7e0?7ff not used figure 5 using internal fpga memory blocks backend interface command legality interface busainen busainp busbinen busbinp busbin busainh busainn busainh busaoutp busboutp busaoutn busboutn core1553BRT-EBR command legality block tx memory write read rx memory read write
core1553BRT-EBR enhanced bit rate 1553 remote terminal 12 advanced v1.1 memory address mapping the core supports an external memory address mapper that allows the rt memory allocation to be easily customized. to use this function, the cmdval output must be latched by the addrlat signal, as shown in figure 6 . then the address mapper function can map the 1553ebr command words, data words including mode code data, and transfer status words to any memory address. interrupt vector extension the core generates a seven-bit interrupt vector that contains the sub-address and whether it was a transmit or receive message. some systems may need to include whether the message was br oadcast, a mode code, or the actual word count in the interrupt vector. the core supports an interrupt vector extension function, similar to the address mapper function using the intlat signal, as shown in figure 7 . figure 6 memory address mapping figure 7 interrupt vector extension q q d l cmdval clk 1553 addrlat memaddr memoper address mapper function mapped address set clr q q d l cmdval clk 1553 intlat intvect interrupt vector extender extended interrupt vector clr set
core1553BRT-EBR enhanced bit rate 1553 remote terminal advanced v1.1 13 status word settings the core1553BRT-EBR sets bits in the 1553ebr status word in complia nce with mil-std-1553b. this is summarized in table 8 . command word storage at the start of every 1553eb r bus transfer, the 1553ebr command word is written to ram locations 000?01f for receive operations and 3e0?3 ff for transmit operations. the addresses are as follows: cmd location rx commands: '000000' and sa cmd location tx commands: '011111' and sa if the rt is implemented without a memory-based backend, the writing of the command word can be disabled (wrtcmd input). th is simplifies the design of the backend logic that dire ctly controls the backend function. transfer status words (tsw) at the end of every 1553e br bus transfer, a transfer status word is written to ram in locations 000?01f for receive operations and 3e0?3 ff for transmit operations. the addresses used are as follows: tsw location rx commands: '000000' and sa tsw location tx commands: '011111' and sa as an example, the tsw addr ess for a transmit command with sub-address 24 would be '01111110100' (3f4h). the tsw contains the information in table 9 on page 14 . if the rt is implemented without a memory-based backend, the writing of the tsw can be disabled. this simplifies the design of the backend logic that directly controls backend functions. backend access times during normal operation, the backend must allow a memory access to complete within 1.0 s. while the status word is being transmitted, the core must write the command word to memory and fetch the first data word. two memory accesses are performed in the 2 s that the status word takes to transmit. at the end of a broadcast-receive command, core1553BRT-EBR writes the last data word and the tsw value before the rt decodes the next command. two memory accesses occur in the 2 s during which the command word is being decoded. the core includes a timer that is set to terminate backend memory access at 1.0 s. table 8 status word bit settings bit(s) function setting 15:11 rt address equals the rtaddr input 10 message error set whenever the rt detects a message error 9 instrumentation always '0' 8 service request controlled by the ssflag input 7:5 reserved always '000' 4 broadcast received set whenever a broadcast message is received 3 busy controlled by the rtbusy input 2 sub-system flag controlled by the ssflag input 1 dynamic bus acceptance always '0'. the core1553BRT-EBR does not operate as a bus controller. 0 terminal flag controlled by the tflag input. if an "inhibit terminal flag" mode code is in effect, will be '0'.
core1553BRT-EBR enhanced bit rate 1553 remote terminal 14 advanced v1.1 1553BRT-EBR operation data transfers ? receive when a receive data transf er command is detected, the core will decode each incoming word. at the end of each word, the core w ill assert memreqn. when memgntn goes low, it will write the da ta word to the memory and release the memreqn. this pr ocess is repeated until the correct number of words has been transferred. the core will then transmit its 1553e br status word. finally, the tsw is also written to memory. data transfers ? transmit when a transmit data transfer command is detected, the core will transmit its status word and assert memreqn. when memgntn goes low, it will read a data word from the memory and release the memreqn. once the word is available, the core will transmit the data word. the core will continue to requ est data from the memory interface until the required number of words has been transferred. finally, the tsw is written to memory. rt-to-rt transfer support the 1553ebr specification (sae as5682) does not support rt-to-rt transfers. likewise, core1553BRT-EBR does not support rt-to-rt transfers. mode codes when the core receives a mode code, it first checks its command validity. if the comma nd is valid, it is processed in accordance with the spec ification. otherwise, the message error bit will be se t in the 1553ebr status word. table 10 on page 15 lists the supported mode codes. two mode codes, (1) transmit a vector word and (2) synchronize with data, require external data. when extmdata is inactive, the vect or word value is set by the vword input and the synchronize with data word is discarded. when extmdata is active, these values are read from and written to memory. the memaddr output will be similar to a single-word data transfer message. bit 10 will reflec t the command word tx bit, and bits 9:5 will be 00h or 1fh, depending on whether the mode code sub-address is set to 0 or 31. bits 4:0 will be zero. this implies that the vector word will be read from location 400h or 7e0h , and the synchronize with data word is written to location 000h or 3e0h, depending on whether sub-address 0 or 31 is used. when both wrtcmd and wr ttsw are active for each message, the command word and tsw value will be written to the same location. these writes can be distinguished by the memoper output. this may cause some system problems, but such can be avoided by implementing an external address mapper function to map these accesses to different addresses. table 9 transfer status word bit(s) name description 15 used this bit is set to '1' at the end of the transmit or receive command. 14 okay indicates that no errors are de tected, i.e., bits 11 to 5 are all '0' 13 busn indicates on which bus the command was received '0': busa '1': busb 12 broadcast indicates a broadcast command 11 lpbkerrb indicates that the loopback logic dete cted an error on the tra nsmitted data for bus b 10 lpbkerra indicates that the loopback logic dete cted an error on the tra nsmitted data for bus a 9 illegal cmd the command was illegal. either a request to trans mit from an illegal sub-address or an illegal mode code was received. 8 memiferr indicates that the dma memory access failed to complete quickly enough 7 manerr indicates that a manchester encoding error was detected in the incoming data 6 parerr indicates that a parity erro r was detected in the incoming data 5 wcnterr indicates that an incorrect number of words was received 4:0 count sa1 to sa31 indicates the number of words receiv ed or transmitted for that sub-address. if wcnterr is '0', '00000' indicates 32 words. otherwise, '00000' indicates zero words transferred. sa0 or sa31 indicates which mode code was receiv ed or transmitted per the 1553ebr specification
core1553BRT-EBR enhanced bit rate 1553 remote terminal advanced v1.1 15 loopback tests the core1553BRT-EBR perfor ms loopback testing on all of its transmission s. the transmit data is fed back into the receiver and each transmitted word is comp ared. if an error is detected, the loo pback fail bit is set in the tsw and also in the bit word. table 10 supported mode codes t/r bit mode code function and effect data word core supports broadcast allowed 1 00000 0 dynamic bus control the core does not support bus controller functions, so it will set the message error and the dynamic bus control bit in the status word. no no no 1 00001 1 synchronize the core will assert its syncnow output after the command word has been received. no yes yes 1 00010 2 transmit status word the core retransmits the last status word. no yes no 1 00011 3 initiate self test the core does not support self test. since the core supports the transmit bit word mode code, this command is trea ted as legal and will not set a message error. no yes yes 1 00100 4 reserved no no no 1 00101 5 reserved no no no 1 00110 6 inhibit terminal flag the core will mask the tflag input and the terminal flag bit in the status word will be forced to zero. no yes yes 1 00111 7 override inhibit terminal flag the core will re-enable the tflag input. no yes yes 1 01000 8 reset remote terminal the core will assert its busreset out put after the command word has been received. it will also reset itself. no yes yes 1 10000 16 transmit vector word the core will transmit a single data word that contains the value on the vword input. yes yes no 1 10010 18 transmit last command word the core will transmit a single data word that contains the last command word received. yes yes no 1 10011 19 transmit bit word the core will transmit a single data word that contains the extended core status information. the value of th is word is defined in table 13 on page 18 . yes yes no 0 10001 17 synchronize with data the core will assert its syncnow output after the data word has been received. yes yes yes 0 10100 20 reserved yes no no 0 10101 21 reserved yes no no
core1553BRT-EBR enhanced bit rate 1553 remote terminal 16 advanced v1.1 error detection table 11 error detection error condition action command word 1. parity or manchester encoding errors 2. incorrect sync waveform command is ignored no interrupt generated mode codes 1. illegal mode code or invalid su b-address from internal or external legality block msgerr in sw is set, and sw is transmitted. message failure interrupt generated broadcast data commands 1. tx bit set in command word data transfer is ab orted. msgerr in sw is set, and sw is not transmitted. message failure interrupt generated data word 1. parity or manchester encoding errors 2. incorrect number of words received 3. data words are continuous 4. incorrect sync waveform data transfer is aborted msgerr in sw is set, and sw is not transmitted message failure interrupt generated transmit data error 1. the rt monitors its transmissions on the bus through its decoder and verifies that the correct data is transmitted with no manchester or parity errors. data transfer is aborted. msgerr in sw is set, and sw is not transmitted. message failure interrupt generated backend failure 1. the rt makes sure that the bac kend responds to read and write cycles within the required time. data transfer is aborted. msgerr in sw is set, and sw is not transmitted. message failure interrupt generated busy 1. backend rtbusy input is active at any point during the messag e. data transfer is aborted. bu sy in sw is set, and sw is transmitted. message failure interrupt generated transmitter overrun 1. transmits for greater than 67 s. the internal state machines prevent this from happening, but the core includes the required timer and functionality. this is implemented separately from the encoder to provide complete protection. core shuts down transmissions on the bus
core1553BRT-EBR enhanced bit rate 1553 remote terminal advanced v1.1 17 built-in test support the core1553BRT-EBR provides a bit word. this is used to communicate fail informat ion back to the bus controller. the bit word contains the information in table 12 . table 12 bit word bit(s) function description 15 businuse indicates on which bus the transmit bit word command was received '0': bus a '1': bus b 14 lpbkerrb indicates that the loopback logic detected an error on the transmitted data for bus b. this bit is cleared by the clrerr input. 13 lpbkerra indicates that the loopback logic detected an error on the transmitted data for bus a. this bit is cleared by the clrerr input. 12 shutdownb indicates that bus b is shutdown. this occurs after a transmitter shutdown mode code is received or the hardware timer detected that the core tra nsmitted for greater than 668 s on bus b. 11 shutdowna indicates that bus a is shutdown. this occurs after a transmitter shutdown mode code is received or the hardware timer detected that the core tra nsmitted for greater than 668 s on bus a. 10 tflaginh terminal flag inhibit setting 9 wcnterr a word count error has occurred. this bit is cleared by the clrerr input. 8 manerr a manchester encoding error has occurr ed. this bit is cleared by the clrerr input. 7 parerr a parity error has occurred. th is bit is cleared by the clrerr input. 6 reserved set to '0' 5 memfail the backend memory interface failed to complete an ac cess within the required time . this bit is cleared in the clrerr input. 4:0 version indicates the core version '01000': ebr version 1.0 (pre-production) '01001': ebr version 2.0
core1553BRT-EBR enhanced bit rate 1553 remote terminal 18 advanced v1.1 command legalization interface 1553ebr commands can be legalized in two ways with the co re1553BRT-EBR. for rtl versi ons, one of the modules in the source code can be edited to legalize or make illega l command words based on the sub-address, mode code, word count, or broadcast fields of the command word. for netlist and rtl versions, external logic may be used to decode the legal/illegal command words (see figure 8 ). the user customization logic block takes in the cmdval and simply sets cmdokay for all legal command words. the cmdval encoding is given in table 13 . the external logic must implem ent this function within 3 s. bus transceivers core1553BRT-EBR drives the 1553ebr bus through standard rs485 transceivers, such as the texas instruments sn65hvd10. typical connections are shown in figure 9 on page 19 . it is recommended that the transceiver used support 3.3 v operation to allow direct conne ction to the 3.3 v i/os on the fpga. typical rt systems the core1553BRT-EBR can be us ed in systems with and without backend memory. figure 9 on page 19 shows a typical implementation for a system with backend memory and a cpu to process the messages. figure 10 on page 19 shows a system with direct connection between the core1553BRT-EBR and external analog-to-digital converters, etc. in this case, any glue logic required between the core and the device being interfaced to can simply be implemented within the fpga containing the core. figure 8 command legalization logic table 13 cmdval encoding bit(s) function description 11 broadcast '1' indicates broadcast, i.e., the rt address was set to 31 in the 1553ebr command word. 10 transmit or receive tx/rx field from the 1553ebr command word. '0' indicates receive and '1' transmit. 9:5 sub-address sub-address field from the 1553ebr command word 4:0 word count mode code word count field from the 1553ebr command word. when the sub-address is 0 or 31, this contains the 1553ebr mode code. core1553BRT-EBR useextok cmdval[11:0] cmdokay user customization logic actel fpga '1'
core1553BRT-EBR enhanced bit rate 1553 remote terminal advanced v1.1 19 figure 9 typical cpu and memory-based rt system figure 10 typical non-memory-based rt system actel fpga memory backend interface command legality interface command legality checker busain busbin busbinenn busbouten busainenn busaouten busaout busbout core1553BRT-EBR rs485 transceivers adc dac glue logic backend interface command legality interface command legality interface busain busbin busbinenn busbouten busainenn busaouten busaout busbout core1553BRT-EBR actel fpga rs485 transceivers
core1553BRT-EBR enhanced bit rate 1553 remote terminal 20 advanced v1.1 specifications memory write timing ? asynchronous mode memory write timing figure 11 memory write timing ? asynchronous mode table 14 memory write timing sync mode description time t pwwr write pulse width (no wait states) 1 clock cycle t pdgnt maximum delay from memreqn to memgntn active 1.2 s t sudata data setup time to memwrn low 1 clock cycle t suaddr address setup time to memwrn low 1 clock cycle t hddata data hold time from memwrn high 1 clock cycle t hdaddr address hold time from memwrn high 1 clock cycle t suwait wait setup to rising clock edge 1 clock cycle valid operation valid data clk memreqn memgntn memcen memcsn memoper memdata memwrn memwaitn memden addrlat valid address memaddr
core1553BRT-EBR enhanced bit rate 1553 remote terminal advanced v1.1 21 memory read timing ? asynchronous mode memory read timing figure 12 memory read timing ? asynchronous mode table 15 memory read timing async mode description time t pwrd read pulse width (no wait states) 1 clock cycle t pdgnt maximum delay from memreqn to memgntn active 1.2 s t suaddr address setup time to memrdn low 1 clock cycle t hdaddr address hold time from memrdn high 1 clock cycle t suwait wait setup to rising clock edge t sudata data setup time to memrdn high valid address memaddr valid operation data clk memreqn memgntn memcen memcsn memoper memdata memrdn memwaitn memden addrlat
core1553BRT-EBR enhanced bit rate 1553 remote terminal 22 advanced v1.1 memory write timing ? synchronous mode figure 13 memory write timing ? synchronous mode address data data written here clk memreqn memgntn memcen memcsn memaddr memdata memwrn memden addrlat memoper operation
core1553BRT-EBR enhanced bit rate 1553 remote terminal advanced v1.1 23 memory read timing ? synchronous mode command word legality interface timing figure 14 memory read timing ? synchronous mode figure 15 command word legality interface timing table 16 command word legality interface timing name description time t pdcmdok maximum external command word legality decode delay 3 s clk addrlat memoper operation address memreqn memgntn memcen memcsn memaddr memden data memdata memrdn data sampled here clk cmdval cmdok cmdstb previous command current command
core1553BRT-EBR enhanced bit rate 1553 remote terminal 24 advanced v1.1 address mapper timing interrupt vector extender timing rt response times rt response time is measured from the midpoint of the parity bit in the command word to the midpoint of the status word sync ( table 17 ). the rt-to-rt timeout is measured from the first command word parity bit to the expected sync of the first data word. note: this figure shows worst-case timing when a second 1553ebr command arrives as the core starts a backend transfer and memgntn is held low. figure 16 address mapper timing note: this figure shows worst-case timing when a second 1553ebr command arrives as the core asserts an interrupt request. also, intla t may be active for several clock cycles prior to intout. figure 17 interrupt vector extender timing clk cmdval addrlat memreqn memcsn current command next command clk cmdval intlat intout current command next command table 17 rt response times spec description time t rtresp rt response time 0.4 to 0.8 s t xxto transmitter timeout 71 s
core1553BRT-EBR enhanced bit rate 1553 remote terminal advanced v1.1 25 transceiver loopback delays core1553BRT-EBR verifies that all transmitted data words are correctly transmitted. as data is transmitted by the transceiver on the 1553ebr bus, it is monitored by the transceiver and decoded by core1553BRT-EBR. the core requires that the loopback delay, i.e., the time from busaout to busain, be less than 180 ns. the loopback delay is a function of the internal fpga delay, pcb routing delays, inte rnal transceiver delay, and transmission effects from the 1553ebr bus. additional register stages may be in serted on either the 1553ebr data input or output within the fpga, providing the required loopback delay is not violated. clock requirements to meet 1553ebr transmission bi t rate requirements, the core1553BRT-EBR clock input must be 100 mhz 0.01%. ordering information core1553BRT-EBR can be orde red through your local actel sales representative. it should be ordered using the following number scheme: core1553BRT-EBR-xx, where xx is listed in table 18 . list of changes the following table lists critical changes that were made in the current version of the document. table 18 ordering codes xx description ev evaluation version sn netlist for single-us e on actel devices an netlist for unlimited use on actel devices sr rtl for single-use on actel devices ar rtl for unlimited use on actel devices ur rtl for unlimited use and not restricted to actel devices previous version changes in current version (a dv an c ed v 1 .1 ) page advanced v1.0 the product name was changed from core1553ebrrt to core1553BRT-EBR. n/a changed "mil-std-1553ebr" to "mil-std-1553b" under "verification and compliance" 1 first bullet added under "verification and compliance" 1 changed "sae air5610" to "sae as5682" under "rt-to-rt transfer support" 14 changed time values in ta b l e 1 7 24 changed maximum loopback delay under "transceiver loopback delays" 25
core1553BRT-EBR enhanced bit rate 1553 remote terminal 26 advanced v1.1 datasheet categories in order to provide the latest information to designers, some datasheets are published before data has been fully characterized. datasheets are designated as "product brief," "advanced," and "production." the definition of these categories are as follows: product brief the product brief is a summarized version of an advanced or production datasheet containing general product information. this brief summarizes specific devi ce and family information for unreleased products. advanced this datasheet version contains initial estimated information based on simulation, other products, devices, or speed grades. this information can be used as estimates, but not for production. unmarked (production) this datasheet version contains informat ion that is considered to be final.

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